Breakthrough technology enables CORBA compliant components to be deployed on a Field Programmable Gate Array
Boston, MA, USA – February 17, 2011 – PrismTech™, a global leader in standards-based, performance-critical middleware, today announced that it has received notice of allowance for issue of a US Patent for its Field Programmable Gate Array (FPGA) IP Core middleware technology – which is today available in its Spectra™ IP Core product for Software Defined Radio (SDR) developers. The patent is expected to issue shortly.
This breakthrough technology allows CORBA®-based application components to be deployed on FPGAs without the use of proxies or other hardware abstraction layers (HALs) that impose additional memory and processing overhead. This provides a significant gain in performance and efficiency – without sacrificing standards compliance or platform independence.
PrismTech’s Spectra IP Core is a firmware implementation of the standard CORBA protocol. By implementing the protocol at the gate-level, key features of a traditional ORB implementation are provided supporting application interoperability, portability and hardware independence through a single, seamless industry-standard data protocol.
Although of general value in the building of distributed embedded systems, the technology was developed primarily to support computationally intensive digital signal processing algorithms deployed in SDR systems complying with the US DoD’s Software Communications Architecture (SCA).
“Spectra IP Core is a revolutionary approach to advancing interoperability and processor transparency across multiple processor architectures within a software defined radio system,” stated Vince Kovarik, SDR CTO, PrismTech. “Spectra IP Core enables a single, common protocol across all processors without compromising the high performance signal processing demands required for high-bandwidth, high-throughput waveforms such as those deployed in satellite communications.”
Elements of the technology covered by the patent include but are not limited to:
- General Inter ORB Protocol (GIOP) protocol machine – a VHDL description of a CORBA GIOP protocol machine.
- Separated Common Data Representation (CDR) encoding machine – a variable encoding machine plug-in such that the GIOP machine may perform encodings other than CDR.
- Open BUS interface – an open architecture to ensure seamless integration with a variety of physical interconnect technologies from the FPGA to the bus arbiter (e.g. when using PCI or VME interconnect) or fabric controller (e.g. when using implementations of the RapidIO standard).
- IDL to VHDL code generation – a set of guidelines to generate VHDL skeletons from CORBA IDL. This enables the GIOP protocol machine to dispatch calls to servants and radio modules developed in an FPGA environment.
- VHDL Component container for use with FPGAs in SDR – using the IDL to VHDL code generator to create a Component container that may be used to host SCA radio elements in an FPGA yet be addressable and callable from a SCA core framework as though it was a standard SCA component.
“PrismTech is very pleased to receive this news of the forthcoming Patent Issue for our Spectra IP Core technology,” said Steve Jennis, SVP Corporate Development and SDR, PrismTech. “Spectra IP Core’s performance is a technology breakthrough and truly brings the FPGA into the SCA domain.”
The Spectra IP Core technology is available today as a COTS product from PrismTech as part of its Spectra product family. Further information about Spectra is available from http://www.prismtech.com/spectra.